When an instruction sequence needs to write data to memory, typically two pieces of information are transmitted to the memory: the command, and the data to be written to memory. It is possible that errors may occur in the transmission of either of these elements. For example, if the command is corrupted, the data may be written to the wrong location in memory. And obviously, if the data is corrupted, then the wrong data may be written to memory.
To address these potential errors, the command and the associated data may be each provided with an error detecting code. Typically, a Cyclic Redundancy Code (CRC) is used. The CRC may then be used by the memory module to determine if there was an error during transmission. If an error is detected, then the memory module may request that the command and associated data be retransmitted.
But transmitting the bits for the CRC takes away from the bandwidth that might be used to transmit commands or data. The number of bits needed to transmit the CRC depends on the specific CRC algorithm implemented. More complicated CRC algorithms are capable of detecting more errors (for example, a simple CRC might detect an error that changes one bit, but not an error that changes two bits), but require more bits to transmit.
Embodiments of the invention address these problems and others in the art.